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RT9629B ? ds9629b-03 october 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? triple-channel synchronous rectified buck mosfet driver general description the RT9629B is a high frequency, triple-channel synchronous rectified buck mosfet driver specifically designed to drive six power n-mosfets. the part is promoted to pair with richtek's multiphase buck pwm controller family for high-density power supply implementation. the output drivers of RT9629B can efficiently switch power mosfets at frequency 300khz typically. operating in higher frequency should consider the thermal dissipation carefully. the device implements bootstrapping on the upper gate with only an external capacitor and a diode required. this reduces circuit complexity and allows the use of higher performance, cost effective n-mosfets. all drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. the RT9629B has also detected the fault condition during initial start-up before the multi-phase pwm controller takes control. as a result, the input supply will latch into the shutdown state. the RT9629B comes in a small footprint package with wqfn-24l 5x5 package. applications z core voltage supplies for desktop, motherboard cpu z high frequency low profile dc/dc converters z high current low voltage dc/dc converters z core voltage supplies for gfx card features z drive six n-mosfets for 3-phase buck pwm control z shoot through protection z embedded bootstrap diode z support high switching frequency z fast output rising time z tri-state pwm input for output shutdown z small 24-lead wqfn package z rohs compliant and halogen free simplified application circuit marking information RT9629Bzqw : product number ymdnn : date code RT9629B zqw ymdnn vccx phase1 RT9629B 12v v out l1 v in l2 phase2 pwm1 pwm2 pwm1 pwm2 gnd l3 phase3 pwm3 pwm3
RT9629B 2 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function pin description pin no. pin name pin function 1, 12, 19 ugate3, ugate1, ugate2 high side gate drive outputs for phase 3, phase 1, and phase 2. connect this pin to the gate of high side power mosfet. 2, 11, 20 boot3, boot1, boot2 bootstrap power pins for phase 3, phase 1, and phase 2. this pin powers the high side mosfet driver. connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. 3, 14, 23, 25 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4, 6, 8 nc no internal connection. 5, 7, 9 pw m3, pw m2, pw m1 pwm signal input. connect this pin to the pwm output of the controller. 10 por power on reset signal. 13, 18, 24 phase1, phase2, phase3 switch nodes of high side driver 1, driver 2, and driver 3. connect this pin to the high side mosfet source together with the low side mosfet drain and the inductor. 15, 17, 22 lgate1, lgate2, lgate3 low side gate drive output for phase 1, phase 2, and phase 3. this pin drives the gate of low side mosfet. 16, 21 vcc1, vcc2 supply input pin. vcc1 supplies current for channel 1 and channel 2 gate drivers. vcc2 supplies current for channel 3 gate driver. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. (top view) wqfn-24l 5x5 pin configurations lead plating system z : eco (ecological element with halogen free and pb free) RT9629B package type qw : wqfn-24l 5x5 (w-type) ugate3 nc gnd boot3 phase2 lgate1 vcc1 lgate2 nc pwm1 por boot1 gnd lgate3 vcc2 boot2 nc pwm3 phase1 gnd pwm2 phase3 ugate1 ugate2 25 gnd 18 17 16 15 1 2 3 4 891011 23 22 21 20 14 13 5 6 7 24 12 19
RT9629B 3 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram shoot-through protection turn off detection shoot-through protection tri-state detect vcc1 pwm1 internal vdd boot1 ugate1 phase1 lgate1 gnd vcc1 por bootstrap control por vcc2 shoot-through protection turn off detection shoot-through protection tri-state detect vcc1 pwm2 internal vdd boot2 ugate2 phase2 lgate2 gnd vcc1 bootstrap control shoot-through protection turn off detection shoot-through protection tri-state detect vcc2 pwm3 internal vdd boot3 ugate3 phase3 lgate3 gnd vcc2 bootstrap control
RT9629B 4 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation por (power on reset) por block detects the voltage at vcc1 pin and vcc2 pin. when the vcc1 and vcc2 pin voltage is higher than por rising threshold, por pin output voltage (por output) is high. por output is low when vcc1 and vcc2 are not both higher than por rising threshold. when the por pin voltage is high, ugatex and lgatex can be controlled by enx pin and pwmx pin voltage. with low por pin voltage, both ugatex and lgatex will be pulled to low. tri-state detect when both por block output and enx pin voltages are high, ugatex and lgatex can be controlled by pwmx input. there are three pwmx input modes, which are high, low, and shutdown state. if pwmx input is within the shutdown window, both ugatex and lgatex output are low. when pwmx input is higher than its rising threshold, ugatex is high and lgatex is low. when pwmx input is lower than its falling threshold, ugatex is low and lgatex is high. bootstrap control bootstrap control block controls the integrated bootstrap switch. when lgatex is high (low side mosfet is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to bootx pin. when lgatex is low (low side mosfet is turned off), the bootstrap switch is turned off to disconnect vccx pin and bootx pin. turn-off detection turn-off detection block detects whether high side mosfet is turned off by monitoring phasex pin voltage. to avoid shoot through between high side and low side mosfets, low side mosfet can be turned on only after high side mosfet is effectively turned off. shoot-through protection : shoot-through protection block implements the dead time when both high side and low side mosfets are turned off. with shoot-through protection block, high side and low side mosfet are never turned on simultaneously. thus, shoot through between high side and low side mosfets is prevented.
RT9629B 5 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit power supply voltage v cc 4.5 -- 13.2 v power supply current i vcc v bootx = 12v, pwmx floating -- 250 -- a power on reset (por) por rising threshold v por_r v ccx rising -- 4 4.4 v por falling threshold v por_f v ccx falling 3 3.5 -- v por pin high voltage v por_h -- 3.5 4 v por pin low voltage v por_l -- -- 0.5 v (v ccx = 12v, t a = 25 c unless otherwise specified) absolute maximum ratings (note 1) z supply voltage, vcc1, vcc2 --------------------------------------------------------------------- ? 0.3v to 15v z bootx to phasex ---------------------------------------------------------------------------------- ? 0.3v to 15v z phasex to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to 30v < 20ns --------------------------------------------------------------------------------------------------- ? 10v to 35v z lgatex to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to (vcc + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- ? 2v to (vcc + 0.3v) z ugatex to gnd dc -------------------------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) < 20ns --------------------------------------------------------------------------------------------------- (v phase ? 2v) to (v boot + 0.3v) z pwmx to gnd ---------------------------------------------------------------------------------------- ? 0.3v to 7v z por to gnd ------------------------------------------------------------------------------------------- ? 0.3v to 5v z power dissipation, p d @ t a = 25 c wqfn-24l 5x5 --------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) wqfn-24l 5x5, ja ---------------------------------------------------------------------------------- 36 c/w wqfn-24l 5x5, jc --------------------------------------------------------------------------------- 6 c/w z lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c z junction temperature -------------------------------------------------------------------------------- 150 c z storage temperature range ----------------------- ------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) -------------------------------------- ----------------------------------- 2kv recommended operating conditions (note 4) z supply voltage, vcc1, vcc2 --------------------------------------------------------------------- 4.5v to 13.2v z junction temperature range ----------------------- ------------------------------------------------ ? 40 c to 125 c z ambient temperature range ----------------------- ------------------------------------------------ ? 40 c to 85 c
RT9629B 6 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit pwm input maximum input current i pwm v pw mx = 0v or 5v -- 160 -- a pwmx floating voltage v pwm_fl pwmx = open -- 1.8 -- v pwmx rising threshold v pwm_rth 2.3 2.8 3.2 v pwmx falling threshold v pwm_fth 0.7 1.1 1.4 v timing ugatex rising time t ugater 3nf load -- 25 -- ns ugatex falling time t ugatef 3nf load -- 12 -- ns lgatex rising time t lgater 3nf load -- 24 -- ns lgatex falling time t lgatef 3nf load -- 10 -- ns t ugatepgh -- 30 -- t ugatepdl v bootx ? v phasex = 12v see timing diagram -- 22 -- ns t lgatepdh -- 30 -- propagation delay t lgatepdl see timing diagram -- 8 -- ns output ugatex drive source r ugatesr v boot ? v phase = 12v, i source = 100ma -- 1.7 -- ugatex drive sink r ugatesk v boot ? v phase = 12v, i sink = 100ma -- 1.4 -- lgatex drive source r lgatesr i source = 100ma -- 1.6 -- lgatex drive sink r lgatesk i sink = 100ma -- 1.1 --
RT9629B 7 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit timing diagram pwmx ugatex lgatex t ugatepdh t lgatepdl t ugatepdl t lgatepdh 90% 90% 1.5v 1.5v 1.5v 1.5v vcc2 pwm1 gnd boot1 ugate1 phase1 lgate1 RT9629B q ug1 12v pwm1 v out q lg1 c vcc c boot1 c ph1 r vcc r boot1 r ug1 r lg1 r ph1 l1 2.2 1f 1 1f 2.2 0 2.2 3.3nf pwm2 pwm2 pwm3 pwm3 boot2 q ug2 q lg2 c boot2 c ph2 r boot2 r ug2 r lg2 r ph2 l2 1 1f 2.2 0 2.2 3.3nf boot3 q ug3 q lg3 c boot3 c ph3 r boot3 r ug3 r lg3 r ph3 l3 1 1f 2.2 0 2.2 3.3nf v in v in c out c in ugate2 phase2 lgate2 ugate3 phase3 lgate3 21 9 7 5 3, 14, 23, 25 (exposed pad) 11 12 13 15 20 19 17 2 24 1 22 vcc1 16 18 por 10 270f x 3 820f x 6 12v v in
RT9629B 8 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics time (20ns/div) dead time no load (5v/div) ugate phase lgate time (20ns/div) pwm rising edge ugate (20v/div) phase (10v/div) pwm (10v/div) lgate (10v/div) time (20ns/div) pwm falling edge ugate (20v/div) phase (10v/div) pwm (10v/div) lgate (10v/div) time (20ns/div) dead time (5v/div) ugate phase lgate full load time (20ns/div) dead time (5v/div) full load ugate phase lgate time (20ns/div) dead time no load (5v/div) ugate phase lgate
RT9629B 9 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (20ns/div) short pulse no load ugate phase lgate ugate ? phase (5v/div)
RT9629B 10 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT9629B is a high frequency, triple-channel synchronous rectified. mosfet driver containing richtek's advanced mosfet driver technologies. the RT9629B is designed to be able to adapt from normal mosfet driving applications to high performance cpu vr driving capabilities. supply voltage and power on reset the RT9629B can be utilized under both v ccx = 5v or v ccx = 12v applications which may happen in different fields of electronics application circuits. in terms of efficiency, higher v ccx equals higher driving voltage of ugatex/lgatex which may result in higher switching loss and lower conduction loss of power mosfets. the choice of v ccx = 12v or v ccx = 5v can be a tradeoff to optimize system efficiency. and vcc1 pin must be directly connected to vcc2 pin. the RT9629B controls both high side and low side n- mosfets of three half-bridge power according to three external input pwmx control signals. it has power on reset (por) function which held ugatex and lgatex low before the vccx voltage rises to higher than rising threshold voltage. when v cc1 and v cc2 exceed the por threshold voltage, the voltage at the por pin will be pulled high. tri-state pwm input after the initialization, the pwmx signal takes the control. the rising pwmx signal first forces the lgatex signal to turn low then ugatex signal is allowed to go high just after a non-overlapping time to avoid shoot through current. the falling of pwmx signal first forces ugatex to go low. when ugatex and phasex signal reach a predetermined low level, lgatex signal is allowed to turn high. the pwmx signal is acted as ? high? if the signal is above the rising threshold and acted as ? low? if the signal is below the falling threshold. when pwm signal level enters and remains within the shutdown window, the output drivers are disabled and both mosfet gates are pulled and held low. if the pwmx signal is left floating, the pin will be kept around 1.8v by the internal divider and provide the pwmx controller with a recognizable level. bootstrap power switch the RT9629B builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate pcb design and reduce total bom cost of the system. hence, no external bootstrap diode is required in real applications. non-overlap control to prevent the overlap of the gate drivers during the ugatex pull low and the lgatex pull high, the non-overlap circuit monitors the voltages at the phasex node and high side gate drive (ugatex ? phasex). when the pwmx input signal goes low, ugatex begins to pull low (after propagation delay). before lgatex is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1v. once the monitored voltages fall below 1.1v, lgatex begins to turn high. by waiting for the voltages of the phasex pin and high side gate driver to fall below 1.1v, the non-overlap protection circuit ensures that ugatex is low before lgatex pulls high. also to prevent the overlap of the gate drivers during lgatex pull low and ugatex pull high, the non-overlap circuit monitors the lgatex voltage. when lgatex goes below 1.1v, ugatex goes high after propagation delay. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs1 or v gs2 is at 12v or 5v, the gate draws the current only for few nano-amperes. thus once the gate has been driven up to ? on? level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down 12v (or 5v) rapidly. it is also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows.
RT9629B 11 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 1. equivalent circuit and waveforms (v cc = 12v) in figure 1, the current i g1 and i g2 are required to move the gate up to 12v. the operation consists of charging c gd1 , c gd2 , c gs1 and c gs2 . c gs1 and c gs2 are the capacitors from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs1 and c gs2 are referred as ? c iss ? which are the input capacitors. c gd1 and c gd2 are the capacitors from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as ? c rss ? the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are shown as below : before driving the gate of the high side mosfet up to 12v, the low side mosfet has to be off; and the high side mosfet will be turned off before the low side is turned on. from figure 1, the body diode ? d 2 ? will be turned on before high side mosfets turn on. before the low side mosfet is turned on, the c gd2 have been charged to v in . thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is gd1 gd1 gd1 r1 dv 12 i = c = c (3) dt t it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v in = 12v, v gs1 = 12v, v gs2 = 12v.the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf, and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf and t r = 30ns, from the equation (1) and (2) we can obtain from equation. (3) and (4) the total current required from the gate driving source can be calculated as following equations. ( ) () g1 gs1 gd1 g2 gs2 gd2 i i i 1.428 0.326 1.754 (a) (9) i i i 0.88 0.4 1.28 (a) (10) =+= + = =+= += by a similar calculation, we can also get the sink current required from the turned off mosfet. == g1 gs1 gs1 gs1 r1 dv c x 12 ic dt t (1) (2) -12 gs1 -9 -12 gs2 -9 1660 x 10 x 12 i 1.428 (a) 14 x 10 2200 x 10 x 12 i 0.88 (a) 30 x 10 == == (5) (6) () -12 gd1 -9 -12 gd2 -9 380 x 10 x 12 i 0.326 (a) 14 x 10 500 x 10 x 12+12 i 0.4 (a) 30 x 10 == == (7) (8) == g2 gs1 gs2 gs1 r2 dv c x 12 ic dt t 12v t t v g2 v g1 v phasex +12v l d 2 s 2 c gs2 g 2 i g2 i gd2 i gs2 c gd2 c gs1 c gd1 i gd1 i gs1 i g1 d 2 v out s 1 v in d 1 gnd g 1 v phasex in gd2 gd2 gd2 r2 v12 dv i c c (4) dt t + ==
RT9629B 12 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. select the bootstrap capacitor figure 2 shows part of the bootstrap circuit of the RT9629B. the v cb (the voltage difference between bootx and phasex on RT9629B) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c boot has to be selected properly. it is determined by the following constraints. figure 2. part of bootstrap circuit of RT9629B in practice, a low value capacitor c boot will lead to the over charging that could damage the ic. therefore, to minimize the risk of overcharging and to reduce the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low-esr capacitor should be used to provide good local de-coupling. it is recommended to adopt a ceramic or tantalum capacitor. power dissipation to prevent driving the ic beyond the maximum recommended operating junction temperature of 125 c, it is necessary to calculate the power dissipation appropriately. this dissipation is a function of switching frequency and total gate charge of the selected mosfet. figure 3 shows the power dissipation test circuit. c l and c u are the ugatex and lgatex load capacitors, respectively. the bootstrap capacitor value is 1 f. figure 3. power dissipation test circuit figure 4 shows the power dissipation of the RT9629B as a function of frequency and load capacitance when v cc = 12v . the value of c u and c l are the same and the frequency is varied from 100khz to 1mhz. figure 4. power dissipation vs. frequency the operating junction temperature can be calculated from the power dissipation curves (figure 4). assume v ccx = 12v, operating frequency is 200khz and c u = c l = 1nf which emulate the input capacitances of the high side and low side power mosfets. from figure 4, the power dissipation is 100mw. thus, for example, with the sop- 8 package, the package thermal resistance ja is 120 c/ w. the operating junction temperature is then calculated as : t j = (120 c/w x 100mw) + 25 c = 37 c (11) where the ambient temperature is 25 c. v in c boot v cb + - bootx v ccx ugatex phasex lgatex gnd vccx pwnx gnd bootx ugatex phasex lgatex RT9629B 1f c l 3nf 20 2n7002 2n7002 12v 12v 1f pwmx c boot 10 por por c u 3nf power dissipation vs. frequency 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 frequency (khz) power dissipation (mw) v cc = 12v c u = c l = 1nf c u = c l = 3nf c u = c l = 2nf
? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. RT9629B 13 ds9629b-03 october 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout consideration figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9629B. the converter operates from 5v to 12v of input voltage. for the pcb layout , it should be very careful. the power circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the location of q ugx , q lgx , lx should be very close. next, the trace from ugatex, and lgatex should also be short to decrease the noise of the driver output signals. phasex signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c vcc should be connected to gnd directly. furthermore, the bootstrap capacitors (c bootx ) should always be placed as close to the pins of the ic as possible. figure 6. synchronous buck converter circuit figure 5. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT9629B, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-24l 5x5 package, the thermal resistance, ja , is 36 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for wqfn-24l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. bootx ugatex phasex lgatex vccx RT9629B gnd c bootx 12v l in c out v in v out c in2 phb83n03lt phb95n03lt lx q lgx q ugx c in + + 12v pwmx pwmx c vcc r vcc 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT9629B 14 ds9629b-03 october 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.250 0.350 0.010 0.014 d 4.950 5.050 0.195 0.199 d2 3.100 3.400 0.122 0.134 e 4.950 5.050 0.195 0.199 e2 3.100 3.400 0.122 0.134 e 0.650 0.026 l 0.350 0.450 0.014 0.018 d a3 a e2 e b e d2 see detail a l 1 a1 w-type 24l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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